Hello,
The ARMv8-A-TRM provides the code snipped shown below, under section K9.5.2 within subsection "Ensuring the visibility of updates to instructions for a uniprocessor":
Assume that the memory, to which the instruction is being written, is Normal, Write-Back, Write-Allocate.
Suppose that the STR instruction encountered a cache-miss. The write buffer consumed the write, to allow the CPU to proceed.
The CPU then went on to execute DCCMVAU, with the write still within the buffer.
How does DCCMVAU affect the pending writes in the write buffer?
Why is an instruction to drain the write buffer not needed between STR and DCCMVAU? (Possibly because DCCMVAU drains the buffer too?)
AArch32 P1 STR R11, [R1] ; R11 contains a new instruction to be stored in program memory DCCMVAU R1 ; clean to PoU makes the new instruction visible to the instruction cache DSB ICIMVAU R1 ; ensures instruction cache/branch predictor discards stale data BPIMVA R1 DSB ; ensures completion of the invalidation ISB ; ensures instruction fetch path sees new instruction cache state BX R1
Thank you,
Amol