Hi,
I want to use a dual core with shared L2 cache. On Core0 I want to run Linux and on Core1 I want to run Bare - Metal. Is it possible to control the L2 cache access in case both Cores want to access the L2 cache at the same time. In that case I want Core1 get prior access...
Thanks
Are you talking about quality of service in case of contention? I.e. prioritizing core0's reads for performance?
If so I don't believe you can do that.
If you are talking about functional ordering, ie making sure that core0 has written a value so core1 can consume it, then the answer is yes. Barriers are your friend here. There is a lot of detailed information in the ARM ARM appendix K10 or a less complete but easier to understand description in the ARMv8-A Programmer's Guide.
Yes I'm talking about quality of service in case of contention. The Bare-Metal-System should be deterministic...
I think it depends on the SoC you use and the cache. On L2C310 cache for example you can lock on master so there is one half of the cache for core0 and one for core1 since it has two master and slave ports, I would expect minimal impact. But if you need to have determinism down to this level you should consider to disable cache in the core1 (at least 2nd level).But I doubt that you can reach determinism on an ARMv8-A CPU.
Another question, the SCU is connected via two AXI master and two AXI slave ports to the L2 cache. Can both cores have access to the L2 cache simultaneous and in case not why I have two master ports?
OK