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PoU (Point of Unification)

Hisenberg

Hi all,

 

When reading the ARMv8 reference manual, it mentions a concept of PoU. My understanding is that, if the every CPU core in a cluster has its own L1 cache, and all clusters share an L2 cache, then the PoU is L2 cache.

1. Is my understanding is correct?

2. If we execute a cache maintenance instruction to clean cache to PoU, does it mean that all the L1 caches in the same cluster as the PEe will be cleaned to L2 and the L2 cache will not be cleaned?

 

Any help will be appreciated.

BR

Thanks.

Parents
  • +1
    1) Yes, in the kind of design you described the PoU would be the L2

    2) Maybe. Some cache ops are broadcast, and some are not. For example:

    IC IALLU - would invalidate *this* core's I cache to the PoU, but wouldn't necessarily affect anyone elses.

    IC IALLUIS - is broadcast to the other cores in the inner-shareable domain. And all those cores will invalidate their i cache to the PoU.

    For operations that take an address, broadcast usually depends on the shareability attributes of the address
Reply
  • +1
    1) Yes, in the kind of design you described the PoU would be the L2

    2) Maybe. Some cache ops are broadcast, and some are not. For example:

    IC IALLU - would invalidate *this* core's I cache to the PoU, but wouldn't necessarily affect anyone elses.

    IC IALLUIS - is broadcast to the other cores in the inner-shareable domain. And all those cores will invalidate their i cache to the PoU.

    For operations that take an address, broadcast usually depends on the shareability attributes of the address
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