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What is the Read ID for a SWD transaction?

The ARM page infocenter.arm.com/.../index.jsp talks about "Idle and Reset" condition and says that 50 clocks and Read ID must be sent. But the Read ID is not described anywhere.

Copy-paste:

Idle and reset

Between transfers, the host must either drive the line LOW to the IDLE state, or continue immediately with the start bit of a new transfer. The host is also free to leave the line HIGH, either driven or tristated, after a packet. This reduces the static current drain, but if this approach is used with a free running clock, a minimum of 50 clock cycles must be used, followed by a READ-ID as a new re-connection sequence.

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