During my experiment with GICv3 using ARM Foundation platform, I tried to set GICD_CTLR value from 0x0 to 0x37 (ARE S/NS + Enable G0, G1S and G1NS)
and I got the surprise to see that the finale value of GICD_CTLR was 0x33. G1S was not enabled.
So I decided to first enable ARE S / NS, and in a second time to enable all groups, since the documentation states that switching ARE from 0 to 1 is
unpredicatable when groups are enabled.
Is this the right way to do or can I enable all 5 bits at the same time, and there is an issue with Foundation ?
Best,
V.
Just a quick addendum to my previous reply: if you're doing this directly in code then you'll want to set the ARE_NS and ARE_S bits and then poll GICD_CTLR.RWP (bit [31]) until it's =0. This guarantees that your write the the ARE bits has completed and that its effects are visible, before you attempt to set any of the enable bits.
I am running foundation with the --gic-v3 flags, and it seems Foundation is supporting the legacy mode (because we can read 0 in GICD_CTLR at boot time).
From your answers, I think I can conclude my second approach (writing ARE_NS & ARE_S, synchro, and then write Enable bits) is the correct one and should be used, even if writing all the bit in one go might work on some devices.
Thank you !