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GICv3: setting G1SEN / G1NSEN in GICD_CTLR

During my experiment with GICv3 using ARM Foundation platform, I tried to set GICD_CTLR value from 0x0 to 0x37 (ARE S/NS + Enable G0, G1S and G1NS)

and I got the surprise to see that the finale value of GICD_CTLR was 0x33. G1S was not enabled.

So I decided to first enable ARE S / NS, and in a second time to enable all groups, since the documentation states that switching ARE from 0 to 1 is

unpredicatable when groups are enabled.

Is this the right way to do or can I enable all 5 bits at the same time, and there is an issue with Foundation ?

Best,

V.