From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:
SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treatedas Non-Cacheable:• all pages marked as Write-Through are treated as Non-Cacheable• if ACTLR.SMP=0, all pages marked as Shared are treated as Non-Cacheable.
SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated
as Non-Cacheable:
• all pages marked as Write-Through are treated as Non-Cacheable
• if ACTLR.SMP=0, all pages marked as Shared are treated as Non-Cacheable.
I am only running on a single core, and I want to enable L1 and L2 caches without enabling the SCU (I have issues with that at the moment).
I tried to set ACTLR.SMP to 1 with the SCU disabled without any success so far (I get memory corruption), so how should I set my MMU to get L1 and L2 caches on ?
I think I need to map my pages with the S bit set to 0, is that correct ?
mwsealey I noticed that I don't have any issue running code in svc mode, but I have a lot of errors that seems L1 cache related into my user mode code.
To test this, instead of switching back to a user application at the exit of my kernel, I jumped back to the usual "svc" entry point, read/fill a 2 Mb array with random stuff and loop forever.
This code runs perfectly.
Do you have any idea or suggestions to think I might focus on that would explain why I get cache errors in kernel mode but not in user mode ?
My kernel is mapped as Section, Normal Memory WB WA, Shared, Global
My apps are mapped as 4k Page Tables, Normal Memory, WB WA Shared, Non Global
Best regards,
Vincent
I replaced my TLBIALLIS by ASID with plain TLBIALLIS and it works... I'll try to understand what's happening with my ASID management.