Hello Community,
I have a question regarding the STMIA instruction in an ARM926EJ-S.
We build a SOC with this core and one of our own modules connected to the DATA-AHB has a bug.
One workaround for this bug is to access four adjacent registers (e.g. 0xB0000050, 0xB0000054, 0xB0000058 and 0xB000005C) of this module with a 32bit wide four beat burst.
(The module must see an address change from 0xB0000050 to 0xB0000054 immediatly after the access to 0xB0000050 and normally a four beat burst to 0xB0000050 should do this.)
Is there a possibility that the STMIA in the code example below is executed as four single NONSEQ accesses from the ARM926EJ-S instead as a four beat burst with HTRANS = NONSEQ, SEQ, SEQ , SEQ?
LDR r0, =0xB0000050
LDR r1, =0x12345678
LDR r2, =0x00000000
LDR r3, =0x00000000
LDR r4, =0x00000000
STMIA r0!, {r1 – r4}
Is there a difference between the code above and the code below regarding the possibility that the STMIA is executed as four single accesses?
LDR r12, =0x00000000
STMIA r0!, {r1 – r3, r12}
Every help welcome.
Thank you.
Best regards
Daniel
Hello Yasuhikokoumoto,
thank you for your answer.
We are licensee of the Core and are able to simulate the behavior of losing the ownership of the bus already in RTL simulation.
But maybe there are some other circumstances which can lead to an similar behavior.
If you are a licensee, then you should address your question directly to the ARM support team. I am sure that they can help.
Going back to your original post, there is no difference in execution timing between the two code sequences which you give.
Hope this helps,
Chris