All,
When I am using the cycle counter in AArch64, I am not getting cycles properly. I have enabled read of pmccntr_el0 in user space using a small kernel module. I have sample code like:
asm volatile("isb;mrs %0, pmccntr_el0" : "=r"(prev)); sleep(1); asm volatile("isb;mrs %0, pmccntr_el0" : "=r"(curr)); delta = curr-prev;
I expected delta to be in the range of 1400000000 as a57 in our design runs at 1400MHz
But I am getting around 32100000 which means the cycle counter frequency is ~3.21MHz
The value of Control register is pmcr=41013001 indicating divider is off.
With Generic timer counter registers, I am getting the values as expected. The below code gives
asm volatile ("isb; mrs %0, cntvct_el0" : "=r" (ts)); sleep (2); asm volatile ("isb; mrs %0, cntvct_el0" : "=r" (te)); asm volatile ("isb; mrs %0, cntfrq_el0" : "=r" (freq)); printf ("Aarch64 %20ld cycles\n", (unsigned long long)(te - ts)); printf (" Frequency = %u\n",freq);
I get count of 512021629 cycles for 2 sec as expected for 256MHz frequency which I got from cntfrq_el0.
cntfrq_el0.
Is there something basic I am missing for PMCCNTR_EL0?
PMCCNTR_EL0?
thanks and regards,
Ravi
I guess in ARM-7 architecture (in A15) this was not the case. The CCNT was counting all the cycles (or divided by 64). Using generic timer is not that accurate. For example, in our design the frequency of timer is 256Mhz and CPU frequency is 1600MHz. So, the counter will be 8 times slower.
In case of X86, the rdtsc keeps incrementing at a constant rate irrespective if CPU frequency scaling etc so that we can depend on that to timestamp measurements.
regards,