Hi,
If the Cache line valid bit in implemented in the Memory along with the Tag RAM, during the initial power-up and reset, cache-invalidation requires each bit of the cache line to be explicitly written to '0' which is a operation of lots of clock cycles.(@ one cycle line per cycle).
Is this correct ?
When is this operation performed?
For a mere 32K cache with 128bits cache line ,
there are 256 cache lines, so 256 clock cycles to invalidate the cache, especially during the boot when the processor clock is usually slow.
The other way to implement is , not making the valid bits as part of the tag memory and implement using the flops which can be reset in 1 cycle. But you loose the opportunity to retain the memory during power-down, power-up.
I just want to know what is the usual behavior for processors