Where is hardware interrupt latency documented for the ARMv8 Cortex-A53?

Need specific references to the hardware interrupt latency for the ARMv8 Cortex-A53.  interrupt latency from when an interrupt is triggered to when the ISR is initially invoked, but not including operating system, kernel, or application latency.

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  • For an A-profile core you'll probably find that the latency is dominated by memory system effects caused by the need to fetch instructions and data from main memory to actually run the handler. The costs involved will include both cache fetches and page-table walks to translate addresses.

    I don't have any data to hand, but you are at least talking about thousands of cycles for anything remotely non-trivial if you miss in the cache. A single cache line miss will be 500-1000 cycles of memory round trip if you miss in the cache and TLB (three serialized fetches - two for the page table lookup, one to fetch the data); exactly how many depends on the ratio of CPU clock to memory system latencies. The architecture effects of the interrupt handling in the CPU itself are likely to be insignificant by comparison.

    HTH,
    Pete

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  • For an A-profile core you'll probably find that the latency is dominated by memory system effects caused by the need to fetch instructions and data from main memory to actually run the handler. The costs involved will include both cache fetches and page-table walks to translate addresses.

    I don't have any data to hand, but you are at least talking about thousands of cycles for anything remotely non-trivial if you miss in the cache. A single cache line miss will be 500-1000 cycles of memory round trip if you miss in the cache and TLB (three serialized fetches - two for the page table lookup, one to fetch the data); exactly how many depends on the ratio of CPU clock to memory system latencies. The architecture effects of the interrupt handling in the CPU itself are likely to be insignificant by comparison.

    HTH,
    Pete

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