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Need to invalidate L1 cache after DMA on Cortex A9

Rohan

Hi,

I'm using a Renesas RZ/A1L, Cortex A9 microcontroller. After a DMA operation which transfers some data from a SPI module into RAM, I can't read the data correctly unless I've disabled L1 cache. (The base code which Renesas supplies sets the caches up initially.)

I suppose what I need to do is tell the processor to invalidate any L1 cache just for the memory region in question (usually 512 bytes). I'm struggling to work out how to do this, despite googling a lot. I've learned about CP15 registers, which do things like enable or disable the cache as a whole, but to invalidate just a small region, I'm completely lost.

Any tips would be most welcome.

  • +1

    Hi,

    you can use DCCIMVAC (i.e. MCR p15,0,<Rd>,c7,c14,1) with Rd which includes the target MVA.

    Best regards.

    Yasuhiko Koumoto.

  • 0 in reply to Yasuhiko Koumoto

    Thanks for that. I gave it a go, and googled DCCIMVAC. I think I actually wanted DCIMVAC, because I didn't want to "clean" the cache, just to invalidate it, since I wanted to then be able to read the actual contents of the memory (cleaning would overwrite the actual memory, right?)

    It still didn't quite appear to work, although I think I've realised that what I'm trying to achieve is actually more complicated. While I want to tell the cache to re-grab the contents of the actual memory (to access what the DMA has written to it), I only want to do this for a potentially very small region - maybe smaller than a whole cache "block", and I don't want to lose whatever else might have been cached (and not written out to the actual memory) in that block too.

    If only there was a way that I could tell the Renesas MCU's DMA module to update the cache for the memory it writes to. There doesn't seem to be a way though, I've scoured the manual.

    And I can't just put the memory in question outside of the cached area, because the function I'm developing needs to be able to receive a pointer to the memory it arranges the filling-up of, and I don't have control over where that is.

    Is there another approach I haven't thought of, besides disabling L1 cache or not using DMA?

  • 0

    Some members at the Renesas forum gave me the info I needed to get this working.

    http://renesasrulz.com/renesas_forum_home/rz/f/180/t/6363.aspx