I asked this question in a different community space but it seemed like this is a more appropriate home.
I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The technical reference manual alludes to accesses being different on a 64 bit system. Do I need to do all of the configurations to set up and read the counters using MSR/MRS commands or is it still required to MCR p15 and configure that way? The manual doesn't explicitly state how to configure the individual counters so and any help would be appreciated.
Hi,
did you read the "ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile (ARM DDI 0487A.i (ID012816))"?
By the document, PMU related registers seem to be handled with MSR/MRS instructions in the 64 bit mode.
Best regards,
Yasuhiko Koumoto.
Thank you for your reply i will look into that document.