I see in the documentation site that ARM offers up some bus functional models to simulate both a 32 and a 64 bit AHB bus master in Verilog RTL.
Where do I find these models, and what is the cost?
I am working to verify a customer's AHB peripheral, and don't really want to write my own bus functional model..
There seem to be a number of options hinted at in the documentation area. One such example:
cmsdk_ahb_fileread_master32.v
gordwait, did you fix the issue?
Essentially, yes. Our company did buy the design kit, and it sounds like the bus functional models are part of it.
I'm waiting for access to the files so I can take a look..
good for you then.