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Verilog bus functional models for AHB master simulation

I see in the documentation site that ARM offers up some bus functional models to simulate both a 32 and a 64 bit AHB bus master in Verilog RTL.

Where do I find these models, and what is the cost?

I am working to verify a customer's AHB peripheral, and don't really want to write my own bus functional model..

There seem to be a number of options hinted at in the documentation area. One such example:

cmsdk_ahb_fileread_master32.v

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  • Hi gordwait

    The "cmsdk" part of that filename means the model comes from ARM's Cortex-M System Design Kit. There is also a similar AHB bus master model in ARM's AMBA Design Kit.

    I don't think either model will be available separately, so you would probably need to be looking to buy the full design kit product, which might be more than you currently need.

    The best way to find out how to get access, and how much it would cost, would be to use the "request more information" links on ARM's website for the pages describing these products. Try the following page and "request" button.

    Cortex-M System Design Kit - ARM

    JD

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  • Hi gordwait

    The "cmsdk" part of that filename means the model comes from ARM's Cortex-M System Design Kit. There is also a similar AHB bus master model in ARM's AMBA Design Kit.

    I don't think either model will be available separately, so you would probably need to be looking to buy the full design kit product, which might be more than you currently need.

    The best way to find out how to get access, and how much it would cost, would be to use the "request more information" links on ARM's website for the pages describing these products. Try the following page and "request" button.

    Cortex-M System Design Kit - ARM

    JD

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