Hi ,
In AHB specs, There is one note as below.
Note
Every slave must have a predetermined maximum number of wait states that it will insert before it backs off the bus, in order to allow the calculation of the latency of accessing the bus. It is recommended, but not mandatory, that slaves do not insert more than 16 wait states to prevent any single access locking the bus for a large number of clock cycles.
we have to care for this while design or in verification, if this scenario has to be checked then ??? If yes then after 16 wait state , slave must be give HREADY high after 16 wait state. Right?
Kindly do needful.
Thanks in advance.
Hi ajoo,
HTRANS can signal BUSY in between transfers in any defined length burst, but not after the final transfer.
BUSY means the master is not yet able to commit to the next transfer in a burst, but if you have signalled an 8-beat burst, and have completed the 8th NONSEQ/SEQ access address phase, there is no "next transfer in the burst" because you have already completed that defined length burst.
So BUSY can be used anywhere during bursts, but a burst can only end on a BUSY transfer if the burst type was undefined length INCR.
JD