Hi ,
In AHB specs, There is one note as below.
Note
Every slave must have a predetermined maximum number of wait states that it will insert before it backs off the bus, in order to allow the calculation of the latency of accessing the bus. It is recommended, but not mandatory, that slaves do not insert more than 16 wait states to prevent any single access locking the bus for a large number of clock cycles.
we have to care for this while design or in verification, if this scenario has to be checked then ??? If yes then after 16 wait state , slave must be give HREADY high after 16 wait state. Right?
Kindly do needful.
Thanks in advance.
Hi ajoo
I have moved your questions to ARM Processors where I hope you will get your answer.
Okay