I have a shared memory in DDR --- shared between two separate ARM execution environments (say A and B) in a heterogeneous compute SoC.
SW on each execution units (A and B) Reads and Writes to this shared location (imagine a array/matrix that is being worked on) --- A Read first followed by Write.
i.e.
A : Read array elements, modify, Write
A : Send IPC message to B
B: Read array elements, modify, Write
B: Send IPC message to A
This continues until a certain condition is satisfied.
What should be the memory attribute and cache operations on A and B.
1. Both A and B can have the shared memory mapped as Write-back with Read-alloc
At both A and B, the SW first "invalidate/flushe" the region before the Read, and after Write does a Clean (to push the data to the memory/DDR) before sending the IPC.
2. Both A and B can have the shared memory mapped as Write-through with Read-alloc
At both A and B, the SW would then just need to "invalidate/flush" the region before Read, and no cache operation is required after Write and before sending the IPC.
What would be the right way to do this ?