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On ARM Cortex-R4F, when I disable instruction and data cache using SCTLR register bits I and C, what happens to MPU region that defines region attribute as cachable (write-back)? Would it be ignored since global cache is disabled or would it result in unk

Bill Coder

On ARM Cortex-R4F, when I disable instruction and data cache using SCTLR register bits I and C, what happens to MPU region that defines region attribute as cachable (write-back)? Would it be ignored since global cache is disabled or would it result in unknown behavior?

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