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cortex A9 multi-core

guqintai

I'm learning cortex-a9 on freescale imx6 platform. How to start multi-core? And how to communicate between cores? I'm confused.

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    Hello guqintai,


    all cpu cores go through the same reset vector and the reset handler is the same.
    You can separate the program sequence by reading the Multiprocessor Affinity Register (MPIDR).
    For example,

    MRC p15,0,r0,c0,c0,5 @ read Multiprocessor ID register
AND r0,r0,#3
CMP r0,#3
BEQ cpu3_routine
CMP r0,#2
BEQ cpu2_routine
CMP r0,#1
BEQ cpu1_routine
B  cpu0_routine

    In order to communicate between cpus, it would be normal the shared area but it should enable dcaches and MMU, and it would be a little difficult.
    The most simplest way would be to use LDREX/STREX instruction, making a semaphore for a mail box.

    Best regards,

    Yasuhiko Koumoto.

Reply
  • 0

    Hello guqintai,


    all cpu cores go through the same reset vector and the reset handler is the same.
    You can separate the program sequence by reading the Multiprocessor Affinity Register (MPIDR).
    For example,

    MRC p15,0,r0,c0,c0,5 @ read Multiprocessor ID register
AND r0,r0,#3
CMP r0,#3
BEQ cpu3_routine
CMP r0,#2
BEQ cpu2_routine
CMP r0,#1
BEQ cpu1_routine
B  cpu0_routine

    In order to communicate between cpus, it would be normal the shared area but it should enable dcaches and MMU, and it would be a little difficult.
    The most simplest way would be to use LDREX/STREX instruction, making a semaphore for a mail box.

    Best regards,

    Yasuhiko Koumoto.

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