Is there an intrinsic limit to the width of the bit banding for peripherals for the
Cortex M3?
EFM32 Giant Gecko seems to have a limit of eight bits - bits 8 to 31 does not seem to work.
Is this normal?
Hi there,
There can be several different reasons that bit band doesn't work:
Please note you don't need to use 8-bit load store instructions to access bit 8 to 31. You can use 32-bit/16-bit/8-bit load store instructions to access bit band (just make sure it is aligned transfer).
The choice of the instruction type affects the actual read write transfer size. If the peripheral only support 32-bit read/write, you should use 32-bit load/store instructions.
regards,
Joseph
Hi,
I understand all that, thanks - My defines were based on the ARM one that you point to, but using the predefined names provided by the EFM32 tools.
I have also tested by using a pointer to do the accesses with, using 32 bit writes - it does the same if you use 8 bit writes, as in the bit alias area, only the bit 0 has any relevance.
I have in the mean time tested the tiny gecko too, and the results are the same - bit banding does not work for bits 8 - 31 in the peripheral registers.
It looks like the implementation is broken.
If you have access to one of the EFM32 starter kits, and the free Silabs tools, you can try it and see for yourself.
It would be interesting to see if there are actually M3 implementations out there that fully support peripheral bit banding.
From: jyiu <community@arm.com>
To: H van Rooyen <shapeshifter_100@yahoo.com>
Sent: Wednesday, March 2, 2016 11:34 AM
Subject: Re: - Cortex M3 peripheral Bit Banding limit?
Cortex M3 peripheral Bit Banding limit?
reply from Joseph Yiu in ARM Processors - View the full discussionHi there, There can be several different reasons that bit band doesn't work:
- Bit band is an optional feature on Cortex-M3/M4. If the option is not implemented, then it won't work. I don't think it is the case here because you said bit 0 to 7 works.
- If the bit band support is handled by C bad macro, it could be a problem of the C macro. An example C macro implementation can be found in ARM application note: Cortex-M3 Embedded Software Development
- MPU configuration blocking bit band alias (I don't think this is the case because it will trigger Memory Management Fault, so you should know that has happened.)
- The bus transfer size used is not supported by the peripheral (see below).
Please note you don't need to use 8-bit load store instructions to access bit 8 to 31. You can use 32-bit/16-bit/8-bit load store instructions to access bit band (just make sure it is aligned transfer).The choice of the instruction type affects the actual read write transfer size. If the peripheral only support 32-bit read/write, you should use 32-bit load/store instructions. regards,Joseph
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