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What is the meaning of a 64 bit aligned stack pointer address?

Murtuza Quaizar

According to ARM Architecture Procedure Call Standard (AAPCS) on the ARMv6-M, and ARMv7-M architecture in  it says:

"Although the processor hardware allows SP to be at any word aligned address at function boundaries, standard programming practice requires C program code to ensure that the SP is at a 64-bit (doubleword) aligned address."

What does it mean that the Stack pointer has to be at a 64 bit aligned address?

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  • 0 Arm Employee Badge in reply to Yasuhiko Koumoto

    That's correct. CCR.STKALIGN only affect exception stack frames.  In Cortex-M0, Cortex-M0+ and Cortex-M7 processors, this bit is fixed to 1 which always ensure that the exception stack frames are double word aligned.

    However, software still have to implemented correctly to be AAPCS compliant.

    regards,

    Joseph

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  • 0 Arm Employee Badge in reply to Yasuhiko Koumoto

    That's correct. CCR.STKALIGN only affect exception stack frames.  In Cortex-M0, Cortex-M0+ and Cortex-M7 processors, this bit is fixed to 1 which always ensure that the exception stack frames are double word aligned.

    However, software still have to implemented correctly to be AAPCS compliant.

    regards,

    Joseph

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