According to ARM Architecture Procedure Call Standard (AAPCS) on the ARMv6-M, and ARMv7-M architecture in it says:
"Although the processor hardware allows SP to be at any word aligned address at function boundaries, standard programming practice requires C program code to ensure that the SP is at a 64-bit (doubleword) aligned address."
What does it mean that the Stack pointer has to be at a 64 bit aligned address?
Hello Joseph Yiu,
thank you for your detailed explanation.
I have been misunderstood.
My understanding had been that the case of CCR.STKALIGN=1 made the stack pointer at interrupt or exceptions aligned to 8 byte boundary.
Best regards,
Yasuhiko Koumoto.
That's correct. CCR.STKALIGN only affect exception stack frames. In Cortex-M0, Cortex-M0+ and Cortex-M7 processors, this bit is fixed to 1 which always ensure that the exception stack frames are double word aligned.
However, software still have to implemented correctly to be AAPCS compliant.
regards,
Joseph