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why some instructions are not required to be  explicitly synchronized ?

shengyu shen

Dear all:

In "ARM® Architecture Reference Manual ARMv8", B2.6.5 Concurrent modification and execution of instructions ,

it says some instructions, such as " B, BL, NOP, BRK, SVC, HVC, and SMC " dont need to be explicitly synchronized to instruction cache, while all other instruction need.

I can understand the latter, but no the case of "B, BL, NOP, BRK, SVC, HVC, and SMC ", can some body explain why?

Shen

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  • 0 in reply to Simon Craske

    Dear Simon:

    Thank you for your answer.

    But it seems you are answering "why we need it be like this", instead of "how can we make it happen".

    So is there any special character of these instructions, such as their encoding, that make the other core either see it or not in its entirety?

    These instructions, just like all others, are of the same 32-bit size, if they can be seen entirely, why can not other instrcutions?

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  • 0 in reply to Simon Craske

    Dear Simon:

    Thank you for your answer.

    But it seems you are answering "why we need it be like this", instead of "how can we make it happen".

    So is there any special character of these instructions, such as their encoding, that make the other core either see it or not in its entirety?

    These instructions, just like all others, are of the same 32-bit size, if they can be seen entirely, why can not other instrcutions?

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