Hi,
I am writing a driver for watchdog timer for my custom platform, what I am observing is, as counter 1st time reaches to zero , then it generates an interrupt and ISR is called
Could any body help in this regard...
If you have time and want to read timer behavior from SP805 manual, it says:
."the Watchdog module is based around a 32-bit down counter that is initialized from the Reload Register, WdogLoad. The counter decrements by one on each positive clock edge of WDOGCLK when the clock enable WDOGCLKEN is HIGH. When the counter reaches zero, an interrupt is generated. On the next enabled WDOGCLK clock edge the counter is reloaded from the WdogLoad Register and the count down sequence continues. If the interrupt is not cleared by the time that the counter next reaches zero then the Watchdog module asserts the reset signal, WDOGRES, and the counter is stopped"
Also"The Watchdog counter is reloaded from the Load Register, WdogLoad, whenever:• the counter reaches zero• the interrupt generation is enabled by setting the INTEN bit in the ControlRegister, WdogControl, when it was previously disabled• an interrupt is cleared by writing to the Interrupt Clear register, WdogIntClr• a new value is written to the Load Register, WdogLoad."
Thanks in advance,
Jam
2. I found that my reset signal is connected to flash controller so that flash start execute in place.
3. When ISR is called 1st timer, I disabled the processor interrupts instead of controller interrupts and hence controller interrupt remain inserted and signal is not routed to processor so ISR is not hit continuously.
Thanks,