Hi, I am using imx6ul board which has cortex a7 processor. I am using ffmpeg .s files which has assembly code to integrate into our project to speed up the code. Here is the ffmpeg code in the file mdct_neon.S.
#include "asm.S".fpu neon
.text.global ff_imdct_half_neonfunction ff_imdct_half_neon //, export=1 push {r4-r8,lr}
mov r12, #1 ldr lr, [r0, #20] @ mdct_bits ldr r4, [r0, #24] @ tcos ldr r3, [r0, #8] @ revtab lsl r12, r12, lr @ n = 1 << nbits lsr lr, r12, #2 @ n4 = n >> 2 add r7, r2, r12, lsl #1 mov r12, #-16 sub r7, r7, #16
vld2.32 {d16-d17},[r7,:128],r12 @ d16=x,n1 d17=x,n0 vld2.32 {d0-d1}, [r2,:128]! @ d0 =m0,x d1 =m1,x
..............................
............................
I am getting bus error when the processor executes vld2.32 {d16-d17},[r7,:128],r12. I know this is a neon assembly instruction. I tried with different compilation flags like
arm-xilinx-linux-gnueabi-gcc -march=armv7-a -mfloat-abi=softfp -mfpu=neon -mno-unaligned-access
arm-xilinx-linux-gnueabi-gcc -march=armv7-a -mfpu=neon -mno-unaligned-access
arm-xilinx-linux-gnueabi-gcc -march=armv7-a -mfpu=neon
But I am unable to resolve this. Can anyone help me to solve this... Thanks
"bus error" in Linux can indicate that you've failed to meet the alignment requirements of the load/store instruction.
The VLD2 you are referencing with ":128" appended to the base register requires that the base address be at least 128-bit aligned.
Are you sure that r7 contains an address that is appropriately aligned (i.e. the four least significant bits are zero) ?
Simon.
Thank you simon...I will check whether it is meeting alignment criteria...