Hello experts,
The Cortex-M7 Lecture is opened on APS (ARM Partner Success) Site.Also, #4 and #5 are described the details of Cortex-M7 pipeline.However, I cannot understand the following parts of the lecture.Could anyone teach me them more clearly in order to be understood well?
[original statements]4つのレジスターファイルがポートの読み出し用、2つのレジスターファイルがポートの書き込み用です。どちらも32bit長です。そして、レジスタファイルは動的にスケジューリングされます。
浮動少数点パイプライン以外インオーダー発行ですが、浮動少数点パイプラインだけはアウトオブオーダー発行です。
[source: 会員限定コンテンツエラー ] (to read, the registration of free is needed)
[translation to English by me]There are 4 register files for the port reading, and 2 register files for the port writing. Both are 32bit widths. Then, these register files are dynamically scheduled.
Cortex-M7 pipeline is in-order issuing other than FPU pipeline, but only FPU pipeline is out-of-order issuing.
[interpretation by me]The former means register renaming and there are 4 registers for read and 2 registers for write.The latter means there are 2 instruction queues. One is for the other than FPU instructions. Another is only for FPU instructions. Then, FPU queue can issue 2 instructions with out-of-order.Is my interpretation correct?
Thank you in advance and best regards,Yasuhiko Koumoto.
Hello everyone,
I have gotten the answer from the author.
As the results, the fact was simple.
Regarding the former, there are 2 pipelines for FPU and the FPU register file has 4 32bit read ports and 2 32bit write ports.
Regarding the latter, integer instructions and FPU instructions can be executed in out-of-order way.
Best regards,
Yasuhiko Koumoto.