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Hi experts,
I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller.
I think Figure 1.2 in the TRM is a good starting point:
CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual: 1.2. Typical system configuration
As far as I can see there are two completely distinct AXI interconnect:
The first one is a "point to point" connection. The second instead goes to the real AXI interconnect which, in addition to L3 memory, is connected to other devices/peripherals.
Is my understanding correct?
If so, a more correct figure could be:
Processor <-> Cache controller <-> AXI interconnect <-> L3 memory
Am I right?
Furthermore I would like to know what type of interconnect are these connection AXI3 or AXI4?
Thank you
Regards
Luke
If so, a more correct figure could be: Processor <-> Cache controller <-> AXI interconnect <-> L3 memory
That is probably representative of most Cortex-A9 based systems. I think what the person intended by "L3 memory" was "the memory system".
Cortex-A9 implements AMBA 3 AXI:
Cortex-A9 MPCore Technical Reference Manual: 1.2.2. Advanced Microcontroller Bus Architecture
Thank you for your reply.
So, if I understand correctly these are two completely separated AXI interconnects, one is Processor <-> Cache controller and the other is Cache controller <-> L3 memory.
Is this correct?
Regarding AXI3/4 I'm quite confused here. In ARM document IHI0022E_amba_axi_and_ace_protocol_spec.pdf (AMBA AXI and ACE Protocol Specification) it is reported that AWUSER/ARUSER signals are:
User signals. Optional User-defined signals in the read/write address channel. Supported only in AXI4.
Anyway, since I'm trying to comprehend Shared bit (Coherent/Non-coherent requests) I've seen that both Cortex-A9 and PL310 use these signals for that purpose.
Could be that Processor <-> Cache controller is AXI4 and Cache controller <-> L3 memory is AXI3?
Am I missing something?
Thanks