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Why do you use Cortex-M?

Hello everyone,

I would like to know why you are using Cortex-M microcontroller.

Why don't you adopt other microcontrollers such as 8-bit, 16-bit or MIPS or x86?

The background is that I plan to write a special article regarding Cortex-M on the Interface which is the monthly magazine of Japan published by CQ publishing. However, I cannot say why Cortex-M should be featured because Cortex-M is already famous and almost common sense of microcontrollers. I would like to get exclusive (or special) meanings to introduce Cortex-M nowadays. Please let me know the significance of Cortex-M.

Thank you and best regards,

Yasuhiko Koumoto.

Parents
  • This is great information and wonderful news!

    The $75 kit really looks great; it's affordable and offers quite a lot of features.

    I think that Renesas would be able to make the Cortex-M7 perform 1.6 times the Cortex-M4, though.

    -But we'll have to wait and see what they come up with.

    Do you know how "wide" their GPIO ports are (eg. 16 pins or 32 pins per port) and when running at 240 MHz, how many clock cycles it takes before a pin changes from low to high or hight to low ?

Reply
  • This is great information and wonderful news!

    The $75 kit really looks great; it's affordable and offers quite a lot of features.

    I think that Renesas would be able to make the Cortex-M7 perform 1.6 times the Cortex-M4, though.

    -But we'll have to wait and see what they come up with.

    Do you know how "wide" their GPIO ports are (eg. 16 pins or 32 pins per port) and when running at 240 MHz, how many clock cycles it takes before a pin changes from low to high or hight to low ?

Children
  • Hello Jens Bauer,

    The width of GPIO is at max. 172 depending on a packaging.

    Almost all functional pins can be configured as GPIOs.

    GPIO is driven by at max. 120MHz and change latency would be 1 cycle.

    If you want the cycles from store execution to GPIO output, I don't know it.

    Best regards,

    Yasuhiko Koumoto.

  • "GPIO is driven by at max. 120MHz and change latency would be 1 cycle"

    This indeed sounds very nice.

    Just to confirm: It will be able to change the value of a single GPIO pin 240000000 times per second ?

    (The reason for me asking, is that I'm very interested in fast parallel data transmission, thus I need a high speed and as many pins as possible).

  • Hello Jens Bauer,

    I think a GPIO pin can keep high by 1 cycle and low by 1 cycle.

    So, It will be able to change the value of a single GPIO pin 60000000 times per second at 120MHz.

    The data width of one transaction is at max. 16 bits.

    Please refer to the following picture.

    Therefore 60MHz 16bit GPIO can get 120MB/sec.

    Best regards,

    Yasuhiko Koumoto.