Hi,
I am currently conducting register scan testing on the MHU (Message Handling Unit) of the Corstone SSE-710 platform.
I have encountered an issue with the INT_EN register (offset 0xF98).
0xF98
According to Arm® Corstone SSE-710 Subsystem Technical Reference Manual (Revision: r0p0)
the R2NR and NR2R fields in this register are documented as Read/Write (RW).
The Problem:
During my functional verification, I found that while the Receiver can read these fields, it is unable to write to them.
Write transactions from the Receiver side do not take effect, and the register value remains unchanged.
My Questions:
Are the R2NR and NR2R fields in the INT_EN register designed to be Write-Only (or Read/Write) exclusively for the Sender?
INT_EN
Does the Receiver have any architectural permission to modify these specific interrupt enable bits, or are they strictly controlled by the initiating side (Sender) to manage the interrupt flow?
Any clarification on the expected access behavior for the MHU register map would be very helpful for my verification process.
Best Regards,
Willy