Unable to switch clock source after setting ACLK_CTRL.CLKSELECT to Clock Gate (Corstone SSE-710)

Hi,

I am currently working with the Arm Corstone SSE-710 platform and have encountered a deadlock issue regarding the ACLK_CTRL register.

According to the Arm® Corstone  SSE-710 Subsystem Technical Reference Manual (Revision: r0p0),

the CLKSELECT field in the ACLK_CTRL register allows switching between different clock sources.

One of the available options is to gate the clock.

The Problem:

Once I set the CLKSELECT field to the Clock Gate option, the system appears to hang, and I am no longer able to modify the ACLK_CTRL register or any other registers.

My understanding is that ACLK serves as the main infrastructure clock for the NIC.

Since all write transactions from either the Host CPU or the Secure Enclave must pass through the interconnect clocked by ACLK (NIC),

gating this clock effectively cuts off the path for any subsequent write operations to the ACLK_CTRL register.

Questions:

1. Is there a hardware-level recovery mechanism (other than a full system reset) to regain control once ACLK has been gated?

2. Is this a known limitation where the software must strictly avoid gating ACLK if further configuration is required?

3. What is the recommended sequence for managing ACLK power states without locking out the Host or Secure Enclave interfaces?

Any insights or technical guidance on how to resolve this would be greatly appreciated.

Best Regards,

Willy