Regarding to ATB spec (ARM IHI 0032C (ID120321)) captured as below,
When ATB master can not respond(e.g. CLK gating), it must assert AFREADY as High.
I think If AFREADY is made by a register, Its reset value must be 1'b1(High).
But AFREADY reset value of CSTFunnel used in our SOC is 1'b0. (Released Information is CoreSight-DK-TM908-r0p1-00rel0)
Could you please If it is intended or some errata exists about it?
If AFREADY is implemented via a register, having a reset value of 0 might cause unexpected wait states for the master. Checking for an errata in CoreSight-DK-TM908 might clarify this behavior.