Hello,
I'm attempting to make use of the processor's cache for memory mapped IO.
In theory, this is possible by explicitely maintaining the cache. That is, before reading from memory mapped IO the according cache lines have to be invalidated (e.g. by making use of DC CIVAC), and after writing the according cache lines have to be flushed resp. cleaned (e.g. by making use of DC CVAC).
From the practical behavior I think that I can conclude that the Cortex-A53 also seems to invalidate the cache line as a result of DC CVAC. From a memory semantics point of view this would be just fine. However, it is hurting performance in some scenarios.
Within the ARMv8 documentation I can't find any signs that DC CVAC is virtually falling back to DC CIVAC. Maybe I misunderstood something as well....
Are there any ideas on that matter?
Thanks,
Mario