We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.
I'm currently developing a Cortex-M0 SoC and using the CMSDK one of the module (cm0_pmu_acg_tsmc180.v) need another module called "TLATNTSCA_X8_A7TULL" but when I have downloaded using the IP it doesn't have any module with that name. Are there any solution for the problem I'm facing?
Yes, for RTL synthesis and physical implementation you need both the TSMC 180 nm A7TULL standard-cell library (with the ICG cell). Otherwise, use your own PDK + its ICG cell and remap the module.
So if i want to run the RTL synthesis and physical implementation i should get the TSMC 180nm A7TULL IP or use another PDK module?
The module cm0_pmu_acg_tsmc180.v references a technology-specific standard cell named:
TLATNTSCA_X8_A7TULL
This cell is not included in the CMSDK package or any publicly available IP from Arm. Instead, it is a process-dependent library cell, most likely from TSMC’s 180nm A7TULL standard cell library. As this is a foundry-specific component, it is not modeled behaviorally in Verilog and thus does not appear in the CMSDK download.
If your objective is simulation only and not gate-level synthesis or physical implementation, you can use the generic model provided at:
<your_cortex_m0_dir>/logical/models/cells/cm0_pmu_acg.v
Important: For synthesis or formal verification, you must replace the simulation model with a technology-specific architectural clock gating cell from your chosen standard cell library. This ensures correct glitch-free behavior on the gated clock output and aligns with physical implementation requirements.