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In the TRM of CA53, I see some descriptions of the encodings for AWIDM and ARIDM, and it's quite clear to distinguish Read & Write transactions from different cores.
But in CA72, I can't find such descriptions.
In my simulation, tt seems that it's not able to distinguish normal memory accesses (read or write) according to transaction IDs, even those from different cores may have same IDs.
Can anyone help explain the such transaction-ID related behaviors in CA72.
Thanks a lot ~
Thanks for your reply.
Sorry I didn't make it clear in my question.
According to the TRM, we can identify the core that generate exclusive transactions or the transactions towards Strongly-ordered or Device type memory by AxIDM,
But for those normal transactions towards the memory which is identified as Non-cacheable ,for example, it seems that we cannot distinguish them just with AxIDM.
But in chapter 7.3.1 of TRM of ca53 (http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500f/CIACAJBI.html sorry I don't know how to paste the link like above), it seem we are able to identify which core generate this kind of transactions.
is there anything wrong with my understanding?
Looking forward to your replay.
Thanks
I think you then hit the point the TRM makes at the end of the section...
The system must not rely on specific values of ARID or AWID that correspond with specific transaction sources or transaction types other than the information described in this section.