How To Access SCTLR_EL1 of Non Secure World From EL3

I found this documentation: https://cs140e.sergio.bz/docs/ARMv8-Reference-Manual.pdf

On page D7-2464, it mentions that SCTLR_EL1 of the Non-Secure world can be accessed from EL3.

I am using ARMv8 FVP.

Can anyone provide guidance on how to access and update SCTLR_EL1 of the Non-Secure world (Linux)  from EL3?

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  • You should probably be getting the Arm Architecture Reference Manual from the Arm website rather than a third-party.

    That's not quite what the quoted section is saying.  When EL3 is using AArch64, SCTLR_EL1 is not banked in hardware.  There's one copy of the register used in both Secure and Non-secure (and later Realm) state.  It's up to EL3 software to save/restore the register when execution moves between Security states.

    There are a small number of hardware banked registers in AArch64, mostly connected to the GIC.  For those hardware banked registers, which copy EL3 "sees" is based on the current value of SCR_EL3.NS.  Note, you'd need an ISB (or other context sync event) between writing the SCR_EL3.NS bit and then accessing the selected bank copy of the register.

    Also note, when EL3 is using AArch32 the equivalent register (SCTLR) is hardware banked.

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  • You should probably be getting the Arm Architecture Reference Manual from the Arm website rather than a third-party.

    That's not quite what the quoted section is saying.  When EL3 is using AArch64, SCTLR_EL1 is not banked in hardware.  There's one copy of the register used in both Secure and Non-secure (and later Realm) state.  It's up to EL3 software to save/restore the register when execution moves between Security states.

    There are a small number of hardware banked registers in AArch64, mostly connected to the GIC.  For those hardware banked registers, which copy EL3 "sees" is based on the current value of SCR_EL3.NS.  Note, you'd need an ISB (or other context sync event) between writing the SCR_EL3.NS bit and then accessing the selected bank copy of the register.

    Also note, when EL3 is using AArch32 the equivalent register (SCTLR) is hardware banked.

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