Integrated Debug Functionality in ARM v8

Hi techguyz,

That is totally dependent on the SoC implementation and which ARMv8-A processor is implemented within that SoC. You can find a good description of which resets affect which parts of the Cortex-A57 in Chapter 2.3.2 of the Cortex-A57 Technical Reference Manual. How the SoC power or reset controller handles these signals is totally up to the silicon vendor (within reason).

I prefer to differentiate the terminology here -- reset is what the core does when reacting to a reset signal, booting is what the software does after reset. The Architecture doesn't actually define "cold" and "warm" resets, it only deals with the concept that the core would be reset and then it starts executing instructions from the Reset Vector Base Address in AArch64 (RVBARADDR signal bus input to each core on our example Cortex-A57) or Reset Vector in AArch32. It is up to software to determine a "cold" or "warm" boot process.

To follow up the answer to your previous question about RMR{_EL3}, the RR bit only requests a reset -- the design of the SoC would determine whether this is "warm" or "cold" boot and what gets reset (core, debug, L2..). You may, therefore, have to configure that power controller or reset controller to program in a new RVBARADDR value, configure the finer implementation defined reset signal actions -- or you may find that it is fixed in the design.

Thanks,

Matt S.

Hi techguyz,

That is totally dependent on the SoC implementation and which ARMv8-A processor is implemented within that SoC. You can find a good description of which resets affect which parts of the Cortex-A57 in Chapter 2.3.2 of the Cortex-A57 Technical Reference Manual. How the SoC power or reset controller handles these signals is totally up to the silicon vendor (within reason).

I prefer to differentiate the terminology here -- reset is what the core does when reacting to a reset signal, booting is what the software does after reset. The Architecture doesn't actually define "cold" and "warm" resets, it only deals with the concept that the core would be reset and then it starts executing instructions from the Reset Vector Base Address in AArch64 (RVBARADDR signal bus input to each core on our example Cortex-A57) or Reset Vector in AArch32. It is up to software to determine a "cold" or "warm" boot process.

To follow up the answer to your previous question about RMR{_EL3}, the RR bit only requests a reset -- the design of the SoC would determine whether this is "warm" or "cold" boot and what gets reset (core, debug, L2..). You may, therefore, have to configure that power controller or reset controller to program in a new RVBARADDR value, configure the finer implementation defined reset signal actions -- or you may find that it is fixed in the design.

Thanks,

Matt S.