a custom bootloader that loads an image from an NVMe device - the NVMe driver makes use of LPI interrupts routed through the GICv3 ITS device. Once the bootloader runs and loads the next image into RAM and executes it, the second image re-initializes the GIC, including the ITS device, however no LPI interrupts are ever delivered after this. I found I am unable to set the LPI enable bit back to 0 in redistributor register, and not sure if this could be part of the issue. How can I set GIC LPI enable bit back to 0？
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Do you have an ITS? And if yes, does the ITS have a mapping for the LPI?
Assuming "yes" to both, then you need to issue a CLEAR command (see 5.3.3 in rev H.b of the GICv3/4 spec)
Thanks, I'll try it.
I have read this chapter. But two things here in my mind?Where does ARM document reset GICR_CTLR.EnableLPIs as part of procedures for enabling reinitialization of LPI interrupts?Where does ARM document that ITS CLEAR command is nassery for GICR_CTLR.EnableLPIs reset?
Sorry, I misread your original post - apologies.
Whether GICR_CTLR.EnableLPIs can be cleared without resetting the GIC is IMPDEF. If you're not able to clear it via software, then it's likely that the GIC hardware you're using doesn't support it.