I am currently working with an ARM N2 processor and encountering an issue regarding the configuration and modification of the Scalable Vector Extension (SVE) vector length in the operating system environment. I am seeking clarification on the following:
Background Information:
We have read the following registers in the system, which indicate a configuration suggesting that the SVE vector length should be 2048 bits:
ZCR_EL3 = 0xf
ZCR_EL2 = 0xf
ZCR_EL1 = 0xf
HCR_EL2.{E2H, TGE} is {1, 1}
This configuration appears to set the vector length to 2048 bits. However, when reading the vector length at EL0 in the OS environment, the reported length is still 128 bits, which seems inconsistent with the configuration provided by ZCR_EL2 (which should apply to EL0).
Questions:
Is our chip limited to supporting only a 128-bit SVE vector length?
Upon checking the system register values, we found that ZCR_EL3, ZCR_EL2, and ZCR_EL1 are all set to 0xf, indicating that the SVE vector length has been configured to 2048 bits. However, when reading the SVE vector length at EL0 (operating system environment), it consistently reports as 128 bits. We would like to confirm whether this behavior is due to hardware limitations of the chip, which might support only a 128-bit vector length.
If the chip supports vector lengths greater than 128 bits, how should we configure or modify the SVE vector length in our system?
Hi arry cou ,
To answer your first question: yes. Quoting the Neoverse-N2 TRM:
The Neoverse N2 core implements a scalable vector length of 128 bits.
To answer your second question: configuring the ZCR_ELx registers is the correct method. However, quoting the Arm ARM:
For all purposes other than returning the result of a direct read of ZCR_EL3, the PE selects the highest supported Non-streaming SVE vector length that is less than or equal to the requested length.
Best regards,
Vincent.
Thank you very much for your detailed response. I have one last question for clarification:
Theoretically, a direct read of ZCR_EL3 should return 128 bits for the Neoverse N2 core. However, when directly reading the ZCR_EL3 register, the value returned is 0xf (2048 bits). This seems inconsistent with the N2 TRM. Does this mean that ZCR_EL3 does not directly represent the hardware-supported SVE vector length?
ZCR_EL3
0xf
Hi arry cou,
The ZCR_EL3 register is used to control (limit) the effective VL. It is not an identification register and ZCR_EL3.LEN resets to an architecturally unknown value.
You could read the effective VL with e.g. the RDVL instruction instead.