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Non aligned access in arm v7 going into exception

typedef struct __attribute__((__packed__))

{

uint8_t    op_code;

uint8_t    flags;

uint32_t   logical_block_addr;

uint8_t    group_num;

uint16_t   tx_length;

uint8_t    control;

} SCSI_READ10_t;

when I am assigning some value to tx_length core is showing some exception. Is the assembly of   tx_length assignment  compiler is putting strh/ldrh(half-byte) instruction throwing error its not 2 byte aligned . But not aligned accesses are enabled. So my question is : -

Q1. Can I access not aligned memory with strh/ldrh (suppose addr :- 0xxxx37) if non aligned accesses are enabled for core ?

Q2. Do compiler take care of these no aligned access and will convert not aligned half word into two  1 byte accesses ?

Parents
  • Hello,

    regarding Q2, GCC (I used ver. 4.9.3) converted ome 16bit access into two 8bit accesses.

    1) source code

    typedef struct __attribute__((__packed__))
    {
      uint8_t    op_code;
      uint8_t    flags;
      uint32_t   logical_block_addr;
      uint8_t    group_num;
      uint16_t   tx_length;
      uint8_t    control;
    } SCSI_READ10_t;
    volatile SCSI_READ10_t x;
    main()
    {
      x.tx_length=0x1234;
    }
    

    2) assembly code compiled

    main:
            mov     r1, #52
            mov     r2, #18
            ldr     r3, .L2
            ldrb    ip, [r3, #7]    @ zero_extendqisi2
            strb    r1, [r3, #7]
            ldrb    r1, [r3, #8]    @ zero_extendqisi2
            strb    r2, [r3, #8]
            bx      lr
    .L3:
            .align  2
    .L2:
            .word   x
            .size   main, .-main
            .comm   x,10,4
    

    Best regards,

    Yasuhiko Koumoto.

Reply
  • Hello,

    regarding Q2, GCC (I used ver. 4.9.3) converted ome 16bit access into two 8bit accesses.

    1) source code

    typedef struct __attribute__((__packed__))
    {
      uint8_t    op_code;
      uint8_t    flags;
      uint32_t   logical_block_addr;
      uint8_t    group_num;
      uint16_t   tx_length;
      uint8_t    control;
    } SCSI_READ10_t;
    volatile SCSI_READ10_t x;
    main()
    {
      x.tx_length=0x1234;
    }
    

    2) assembly code compiled

    main:
            mov     r1, #52
            mov     r2, #18
            ldr     r3, .L2
            ldrb    ip, [r3, #7]    @ zero_extendqisi2
            strb    r1, [r3, #7]
            ldrb    r1, [r3, #8]    @ zero_extendqisi2
            strb    r2, [r3, #8]
            bx      lr
    .L3:
            .align  2
    .L2:
            .word   x
            .size   main, .-main
            .comm   x,10,4
    

    Best regards,

    Yasuhiko Koumoto.

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