Cortex-m7 Cache prefetching

The ARM architecture provides memory system hints PLD (Preload Data) and PLI (Preload instruction) to permit software to communicate the expected use of memory locations to the hardware. The effect of these memory system hints is IMPLEMENTATION DEFINED. Typically, implementations will use this information to bring the data or instruction locations into caches that have faster access times than Normal memory.

The PLD will preload a single cache line, customers using Cortex-M7 may write software that makes use of the PLD instruction for preloading the data cache (the D-cache must be enabled in order for this to take effect).

NOTE: PLI will be treated as a NOP on Cortex-M7.

Caches are typically populated during runtime from the natural execution of code, and accesses of Normal, Cacheable memory locations (cache misses generate cache linefills). Note, the Cortex-M7 has a 4x64-bit instruction queue.

There are no RTL build time parameters that impact the capability of prefetching data using PLD on Cortex-M7.

The Cortex-M7 does support preloading of the TCMs during runtime and before releasing reset. Please refer to the following documentation:

https://developer.arm.com/documentation/ddi0489/f/BABCACCF

The ARM architecture provides memory system hints PLD (Preload Data) and PLI (Preload instruction) to permit software to communicate the expected use of memory locations to the hardware. The effect of these memory system hints is IMPLEMENTATION DEFINED. Typically, implementations will use this information to bring the data or instruction locations into caches that have faster access times than Normal memory.

The PLD will preload a single cache line, customers using Cortex-M7 may write software that makes use of the PLD instruction for preloading the data cache (the D-cache must be enabled in order for this to take effect).

NOTE: PLI will be treated as a NOP on Cortex-M7.

Caches are typically populated during runtime from the natural execution of code, and accesses of Normal, Cacheable memory locations (cache misses generate cache linefills). Note, the Cortex-M7 has a 4x64-bit instruction queue.

There are no RTL build time parameters that impact the capability of prefetching data using PLD on Cortex-M7.

The Cortex-M7 does support preloading of the TCMs during runtime and before releasing reset. Please refer to the following documentation:

https://developer.arm.com/documentation/ddi0489/f/BABCACCF