We have a few security blocks along the way and we use Axuser to carry the security settings like Stream ID etc.
There is a security block in front of masters where they are supposed to change the User bits based on realms.
These security blocks should not add latency and hence do not implement a proper register slice (accept Axi and send Axi)
They combinatorially decide the User bits and send it out on the bus.
So is it okay that master sends say X and the block inbetween converts that to Y before mapping it to slave.
There is a slight rule we are possibly breaking where AxUser bits changing whilst valid is asserted ? Is that okay.
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