Hi everyone,
I'm trying to find an answer to my question in the previous posts, but I haven't found it.
I have an "academic" question about Cortex-M4 architecture: considering the typedef variable names in the stdint library (uint32_t, int32_t, uint8_t, etc.) in a Cortex-M4 what is the variable type to archive the fastest write/read access way?
In other words, if I use a 8-bit variable as "flag" variable, a 32-bit MCU (as Cortex-M4) needs additional operational (e.g.: hardware mask, etc.) to manage a 8-bit variable instead of a "native" 32-bit variable?
Thank you,
> if I use a 8-bit variable as "flag" variable, a 32-bit MCU (as Cortex-M4) needs additional operational (e.g.: hardware mask, etc.) to manage a 8-bit variable instead of a "native" 32-bit variable?
It depends. If the word (32-bit data) holding the a byte flag (8-bit data) has any other valid data that is used by your program, yes, you must perform additional operations to not destroy these data (i.e. other 24-bit data). It's usually achieved by a read-modify-write i.e. Read a word, Modify only one byte (in the word), then Write the word. If your target system is a multi-core system, you must also consider exclusive access so that while one core is performing a read-modify-write to the data, other core(s) won't destroy it.
FYI, some M-profile core's TRM define machine cycles for each instruction. For Cortex-M4, please see the TRM below.
developer.arm.com/.../Table-of-processor-instructions
For example, STR (Word store), STRH (Halfword store), and STRB (Byte store) consumes the same machine cycles i.e. 2 cycles so storing 32-bit and storing 8-bit take the same cost. And, same is true for load instructions such as LDR, LDRH, and LDRB.
Kind regards,
Toshi
Thanks Toshi,
Your answer - and the link reported - it's very useful in order to understand thoroughly.
Regards,
Flavio