This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Read memory block loaded by bootloader at EL3, but on EL2

Hi Everyone,

I'm developing a bare-metal application to run on an ARM Cortex A53 core. 

I'm using u-boot compiled with the respective flags to start the application at EL3, so that we have full control of the processor configuration.

Right now, I'm trying to read a memory block of 181 bytes at address 0x8028000 while on EL2 but, most of the times, the processor is reading what looks like a memory block with some corrupted bytes.

The EL3 registers are configured as follows:

TCR_EL3 - 0x80823518

MAIR_EL3 - 0x000000ff440c0400

SCTLR_EL3 - 0x00C5183D

the L0 table (at address 0x8000c000):

0x8000c000:     0x000000008000d003      0x0000000000000000
0x8000c010:     0x0000000000000000      0x0000000000000000

the L1 table

0x8000d000:     0x000000008000e003      0x000000008000f003
0x8000d010:     0x0000000080000611      0x00000000c0000611
0x8000d020:     0x0000000000000000      0x0000000000000000

As I understand, address 0x80280000 would match index 0 and index 2 of table L0 and L1 respectively, which will lead to a block descriptor that configures the access to the 1GB block.

Also, analyzing the NS bit of the Table (bit 63) and Block (bit 5)  descriptors, we can see that those accesses are being translated into secure IPA or PA space.

I've tried to configure both descriptors to have the NS bit enabled and configured the EL2 MMU to access the block I wanted, but failed to read it without corruption.

Does anyone have a suggestion as to what I might be missing?

Thanks in advance.

Kind Regards,

pcarmo

Parents
  • If I'm reading your values correctly, the region of memory is marked as Normal Write-Back Cacheable for EL3, and EL3 has the MMU and caches enabled.

    So question... do you have the same cache ability set up in EL2?  (i.e. same decriptior/MAIR/SCTLR set up)

Reply
  • If I'm reading your values correctly, the region of memory is marked as Normal Write-Back Cacheable for EL3, and EL3 has the MMU and caches enabled.

    So question... do you have the same cache ability set up in EL2?  (i.e. same decriptior/MAIR/SCTLR set up)

Children