Hi there
Im working on a cycloneVsoc board with a cortex a9 duel core HPS.
I found out my load was too heavy for one core. And I researched a lot for duel core solutions. It turns out that there is little about how to use the duel core for cortex a9 in baremetal system.
I would like to use AMP mode for my board and run a baremetal/baremetal system.
I see my CPU0 as main CPU
and looking forward it to do the following job:
1. initial the system (include fpga image ,fpga bridges and interrupts, some service code and a simple scheduel tactic) ------- done
2. copy the CPU1 image (bin file with the same initial code, I don't know if it is necessary) -------- don't know how to do it(Assambly ?)
3. tell the CPU1 its start address and shared RAM --------- could be done as a struct.
4. wake up the CPU1 from CPU0 ---------- no idea at all
5. getting into CPU state machine and let the machine run , two CPUs will repond the same FPGA IRQ signal and do different tasks. ---------- which is the main goal for my design.
The main issue is how to write the image file to the exact address (during debug and/or make it as one image).
And how to wake up the CPU1 from CPU0.
And if you find out my struct has any kind of potancial issues, please let me know.
Very thank you for your kindly help.
Reguards
Alex
There are likely device specific considerations. It would be best to ask on the Intel forums.https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/bd-p/fpga-soc-cpld-boards-kits
For a generic answer, see the `Fireworks_A9-FVP_AC6` example provided with Arm Development Studio, which includes similar initialization code.
Thank you for your help.
Unfortunately, the intel guys suggest me to ask you guys for they do not have software support for baremetal ones.
I'll check the material you mentioned.
I would be appreciative if you could give me more information about the duel core baremetal with AMP system.
I looked through the PG but still dont know where to start.
Again,
thank you for your help.
Best reguards