I have a problem with my custom IP. The idea its that i reply the behaviour of the BRAM CONTROLLER defined on the IP catalog of the Xilinx tool.
The new behaviour its that i can define a different width, for example having a 128 bits on the AXI width an 64 bits on the side of the memory (BRAM).
My problem its when i am running all of the cores available on the KRIA KV260 (Zynq Ultrascale + family), i am see this warning
Search on the internet they said that its related to a ATB register associate with the time out of the AXI, but i can understand what i am have to modify.
If someone have any idea to solve this problem pls help me! thx!
I can't help with your question, but probably because this sounds more like a question you should be asking on a Xilinx discussion forum. I don't think there is anything specific to AXI in your question.
OK, do you know how an axi slave works if there have different width between the axi and the bram???. My principal problem if when i am doing a reading its necesary to register the RID signal or its only a stamp??
If the AXI slave's data bus width is 128 bits and the BRAM is 64 bits, the AXI slave will have to perform some downsizing of wider transfer requests so one AXI read generates 2 BRAM reads which the AXI slave will then merge together to give you the requested 128 bit read data.
For the RID question, RID needs to be driven to the same value the ARID request used. If the ARID request would result in a burst of AXI read transfers, each AXI read transfer will need to use this same RID value.
IDs are used to link data transfers and responses (for writes) to the original transfer request. If you don't return the correct RID or BID value, the AXI interconnect logic won't know which request these responses relate to.