Cortex-M7 "zero overhead loop"

Hi,

There is no new/special instruction for loops in Cortex-M7.

The design help reducing loop overhead in a number of ways:

- BTAC enable good accuracy in branch predction, so in most cases, there is no branch penalty (of course you still got branch penalty if the prediction is wrong)

- a branch instruction can execute at the same cycle with another data processing instruction

- moving the condition generation instruction eariler helps in some cases too (but in general the design of Cortex-M7 enable high performance without too much of compiler optimization).

So in strictly computer "geek" language, I won't call it zero-over-head loops . But the result is essentially same as some zero-overhead-loop designs, so in "PR" language this description is "correct".

And Ari is right that there is no BTAC in Cortex-M4.

regards,

Joseph

(Disclaimer : this message is written before my 2nd cup of coffee this morning....may not be suitable for human consumption).

Hi,

There is no new/special instruction for loops in Cortex-M7.

The design help reducing loop overhead in a number of ways:

- BTAC enable good accuracy in branch predction, so in most cases, there is no branch penalty (of course you still got branch penalty if the prediction is wrong)

- a branch instruction can execute at the same cycle with another data processing instruction

- moving the condition generation instruction eariler helps in some cases too (but in general the design of Cortex-M7 enable high performance without too much of compiler optimization).

So in strictly computer "geek" language, I won't call it zero-over-head loops . But the result is essentially same as some zero-overhead-loop designs, so in "PR" language this description is "correct".

And Ari is right that there is no BTAC in Cortex-M4.

regards,

Joseph

(Disclaimer : this message is written before my 2nd cup of coffee this morning....may not be suitable for human consumption).