Cortex-M7 "zero overhead loop"

Zero-overhead-loop has nothing to do at all with branches. It is a well known technique widely used in DSPs. Almost every decent DSP that I used had this function in it.

To make zero-overhead-loop work two things are needed: (1) a "loop" instruction that tells the processors the number of iterations to process (there are other fancy, mostly academic, techniques that can do without a dedicated loop instruction but I have never seen them used in a commercial processor) and (2) an optional loop buffer to store the loop instructions depending on the processor instruction memory configuration. When the loop instruction is decoded by the processor the number of iterations is loaded into a loop counter that automatically counts down until it reaches zero and the loop terminates. The updating of the loop counter is down in parallel with the execution of the loop instructions and therefore doesn't consume any additional CPU cycles thus "zero-overhead-loop". A branch instruction on the other hand will consume multiple cycles (condition check which might take several to execute plus the branch itself). Hope this explanation clarifies the difference between zero-overhead-loops and branches.

Now, considering that the Cortex-M7 doesn't have a loop instruction (I searched infocenter.arm.com for "cortex-m7 zero overhead loop" and got 0 hits so I am relying on the other comments in the post) then it should not claim that it supports zero-overhead-loop. I am not that familiar with the Cortex-M7 as some processors have separate instructions to load the loop counter and then a regular unconditional branch instruction which gets executed only once at the start of the loop. Might need to ask ARM to clarify what exactly is meant by "zero-overhead-loop". The alternative is just ignore that marketing doc and rely on the programmers manual which is more accurate.

Zero-overhead-loop has nothing to do at all with branches. It is a well known technique widely used in DSPs. Almost every decent DSP that I used had this function in it.

To make zero-overhead-loop work two things are needed: (1) a "loop" instruction that tells the processors the number of iterations to process (there are other fancy, mostly academic, techniques that can do without a dedicated loop instruction but I have never seen them used in a commercial processor) and (2) an optional loop buffer to store the loop instructions depending on the processor instruction memory configuration. When the loop instruction is decoded by the processor the number of iterations is loaded into a loop counter that automatically counts down until it reaches zero and the loop terminates. The updating of the loop counter is down in parallel with the execution of the loop instructions and therefore doesn't consume any additional CPU cycles thus "zero-overhead-loop". A branch instruction on the other hand will consume multiple cycles (condition check which might take several to execute plus the branch itself). Hope this explanation clarifies the difference between zero-overhead-loops and branches.

Now, considering that the Cortex-M7 doesn't have a loop instruction (I searched infocenter.arm.com for "cortex-m7 zero overhead loop" and got 0 hits so I am relying on the other comments in the post) then it should not claim that it supports zero-overhead-loop. I am not that familiar with the Cortex-M7 as some processors have separate instructions to load the loop counter and then a regular unconditional branch instruction which gets executed only once at the start of the loop. Might need to ask ARM to clarify what exactly is meant by "zero-overhead-loop". The alternative is just ignore that marketing doc and rely on the programmers manual which is more accurate.