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Cortex-A8 boot up cpsr status

Harshdeep

Hi,

I have a beaglebone black and running a very basic app using starterware. As soon as the app starts executing i copy the CPSR values in memory. The value of CPSR is super surprising

6000019f

which means it is in SYS mode and IRQ, ABORT disabled and FIQ enabled.

i read in the PG that

A processor enters Supervisor mode on Reset.

Really confused

Here is my code for reference

MRS r0, CPSR
LDR r1,=0x800a0000
STR r0, [r1]
ADD r0, r0, #1
LDR r1,=0x800a0004
STR r0, [r1]
LDR r0, =0xDEADBEEF
LDR r1,=0x800a0008
STR r0, [r1]
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    I discoved that in the starterware the bootloader puts the processor in sys mode, so the val 0x6000019f makes sense.

    I tried to read the cpsr right when bootloader is invoked by the public ROM(public ROM is the first piece of instructions that the core executes)

    it read 60000193 - SVC mode but I disabled but F enabled.

    Now in the arm documentation processor enters SVC mode with I and F both disabled.

    Its sad i can't verify that.

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  • 0

    I discoved that in the starterware the bootloader puts the processor in sys mode, so the val 0x6000019f makes sense.

    I tried to read the cpsr right when bootloader is invoked by the public ROM(public ROM is the first piece of instructions that the core executes)

    it read 60000193 - SVC mode but I disabled but F enabled.

    Now in the arm documentation processor enters SVC mode with I and F both disabled.

    Its sad i can't verify that.

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