Hi, I make a software for Cortex-A9 and Cortex-M4 (both uni-processor system).
Question.
Is 64bit-aligned STRD(64bit memory access) atomic ?
(I know tha It is not atomic, but i don't know behavior.)
For example:
LDR R2,=buff
mov R0, #1
mov R1, #2
STRD R0, R1, [R2]
mov R0, #3
mov R1, #4
STRD R0, R1, [R2] <- interrupt occerd
handler:
LDR R0, R1, [R2] <--- ???
Is[R0,R1] == [#3, #2] may?
If it is, require disable-interrupt between STRD?
Thanks for answer.
I need a atomic 'long long' access.
for A9/M4, GCC may output 'LDRD/STRD instruction' for long long.
and typically, long long variable is aligned by 8bytes.
But, if LDRD/STRD is interrupted, must be intterupt-disable for ATOMIC-access?
Hello,
why don't you use STM and ACTLR, disabling the interrupt abort of STM?
It enables more than 64 bit atomic write.
Best regards,
Yasuhiko Koumoto.
OK
I consider.
Thank you.