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STRD ATOMIC?

loquat

Hi, I make a software for Cortex-A9 and Cortex-M4 (both uni-processor system).

Question.

Is 64bit-aligned STRD(64bit memory access) atomic ?

(I know tha It is not atomic, but i don't know behavior.)

For example:

LDR R2,=buff

mov R0, #1

mov R1, #2

STRD R0, R1, [R2]

mov R0, #3

mov R1, #4

STRD R0, R1, [R2]   <-  interrupt occerd

handler:

LDR R2,=buff

LDR R0, R1, [R2]  <--- ???

Is[R0,R1] == [#3, #2] may?

If it is, require disable-interrupt between STRD?

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  • 0

    ldrd/strd are not atomic on Cortex-M4/A9. But at least ldrexd/strexd are.

    DDI 0406c A3.5.3   Atomicity in the ARM architecture

    "Memory accesses caused by a LDREXD/STREXD to a doubleword-aligned location for which the STREXD succeeds

    cause single-copy atomic updates of the doubleword being accessed."

    ARM suggest using ldrexd/strexd to read atomic, but I am pretty sure this works as well:

    ldrexd r0,r1,[r2]

    clrex

    To write atomically, you need to use the "normal" ldrexd/strexd sequence as described in the manual.

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  • 0

    ldrd/strd are not atomic on Cortex-M4/A9. But at least ldrexd/strexd are.

    DDI 0406c A3.5.3   Atomicity in the ARM architecture

    "Memory accesses caused by a LDREXD/STREXD to a doubleword-aligned location for which the STREXD succeeds

    cause single-copy atomic updates of the doubleword being accessed."

    ARM suggest using ldrexd/strexd to read atomic, but I am pretty sure this works as well:

    ldrexd r0,r1,[r2]

    clrex

    To write atomically, you need to use the "normal" ldrexd/strexd sequence as described in the manual.

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